About Me
Hi! I am a computer architecture and systems researcher — a Ph.D. candidate at Seoul National University (SNU, Ph.D. expected Feb. 2027), advised by Professor Jung Ho Ahn, and currently a visiting scholar at the University of Illinois Urbana-Champaign (UIUC) working with Professor Nam Sung Kim. Before joining SNU, I completed my B.S. in Electrical and Electronics Engineering at Chung-Ang University (CAU).
My research focuses on memory systems for AI workloads. I have extensive hands-on experience in real-hardware DRAM characterization (FPGA-based test platforms for DDR4/DDR5/HBM), memory controller design and simulation, and memory-system architecture for LLM inference, recommendation, and GNN workloads. I led the design of RoMe (HPCA’26), a row-granularity memory system for LLM serving, and DRAMScope (ISCA’24), which reverse-engineers DRAM microarchitecture from commodity chips; I co-designed ARC (MICRO’26), an adaptive hotness monitoring unit for CXL tiered memory.
I have 15 publications at ISCA, HPCA, ASPLOS, MICRO, and IEEE S&P, and 10 patent applications (US, CN, PCT, KR). My research goal: make memory the accelerator, not the bottleneck, for large-scale AI.
For more details, please refer to my CV.
Experience
University of Illinois Urbana-Champaign
Visiting Scholar (Prof. Nam Sung Kim)
Oct. 2025 – Present
- CXL tiered memory — co-designed ARC (MICRO’26), a reconfigurable CXL hotness-monitoring unit implemented in RTL on an Altera Agilex CXL device with an Intel Xeon host; up to 24.9% speedup over static trackers with 28.2% less area
- RowHammer mitigation — co-designed PVAC (ISCA’26), a victim-row-based scheme that cuts the overhead of per-row activation counting
- DRAM reliability — running FPGA-based error characterization on commodity DRAM to guide stronger but cost-effective ECC design
Seoul National University, SCALE Lab
Graduate Research Assistant (Prof. Jung Ho Ahn)
Mar. 2021 – Present
- Memory systems for LLM inference — led RoMe (HPCA’26), a row-granularity access memory system for memory-bound LLM serving; 2 KR patents on HBM control filed
- Real-hardware DRAM characterization — built an FPGA-based platform that issues raw commands to DDR4/DDR5 chips and reverse-engineered internal organization and error behavior of DRAMs from major vendors (X-ray, CAL’23; DRAMScope, ISCA’24); validated RowHammer attacks and defenses on real devices (Marionette, ASPLOS’25; TAROT, ASPLOS’24; S&P’26 SoK)
- Near-data processing for AI — co-designed CXL-based NDP for recommendation embedding layers (CLAY, ICS’24) and GNN inference (GraNDe, TC’23)
Samsung Electronics, Memory Division
Research Intern
Nov. 2024 – Feb. 2025
- Modeled a DDR5 memory controller in simulation as part of a CXL memory controller design, covering command scheduling and DRAM timing behavior
- Evaluated design choices (scheduling policies, timing parameters) on memory-intensive workloads to analyze bandwidth and latency trade-offs
Samsung Electronics, Memory Division
Research Intern
Jul. 2023 – Aug. 2023
- Conducted hands-on experiments on an FPGA platform attached to HBM-PIM (processing-in-memory) devices
- Ran and profiled memory-bound kernels to characterize the performance and programming model of PIM offloading
Education
Seoul National University
Mar. 2021 – Feb. 2027 (expected)
Ph.D. in Intelligence and Information Convergence
Advisor: Prof. Jung Ho Ahn
Chung-Ang University
Mar. 2015 – Feb. 2021
B.S. in Electrical and Electronics Engineering
Military service, Republic of Korea, Jul. 2016 – Apr. 2018
Publications
MICRO 2026
ARC: Adaptive Reconfigurable CXL Hotness Monitoring
C. Song, Hwayong Nam, H. Wang, E. Na, H. Park, T. Lee, J. Ahn, N. S. Kim
ISCA 2026
PVAC: A RowHammer Mitigation Architecture Exploiting Per-Victim-Row Counting
J. Kim, S. Baek, Hwayong Nam, M. Wi, N. S. Kim, J. Ahn
IEEE S&P 2026
SoK: Systematizing a Decade of Architectural RowHammer Defenses Through the Lens of Streaming Algorithms
M. J. Kim, S. Baek, J. Kim, Hwayong Nam, N. S. Kim, J. Ahn
HPCA 2026
RoMe: Row Granularity Access Memory System for Large Language Models
Hwayong Nam, S. Baek, J. Kim, M. J. Kim, J. Ahn (*equal contribution)
arXiv 2025
The New LLM Bottleneck: A Systems Perspective on Latent Attention and Mixture-of-Experts
S. Yun, S. Park, Hwayong Nam, Y. Lee, G. Lee, K. Kyung, S. Kim, N. S. Kim, J. Kim, H. Kim, J. Cho, S. Baek, J. Ahn
IEEE CAL 2025
Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads
J. Kim, S. Baek, M. Wi, Hwayong Nam, M. J. Kim, S. Lee, K. Sohn, J. Ahn
ASPLOS 2025
M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems
Y. Sun, J. Kim, Z. Yu, J. Zhang, S. Chai, M. J. Kim, Hwayong Nam, J. Park, E. Na, Y. Yuan, R. Wang, J. Ahn, T. Xu, N. S. Kim
ASPLOS 2025
Marionette: A RowHammer Attack via Row Coupling
S. Baek, M. Wi, S. Park, Hwayong Nam, M. J. Kim, N. S. Kim, J. Ahn
ISCA 2024
DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands
Hwayong Nam, S. Baek, M. Wi, M. J. Kim, J. Park, C. Song, N. S. Kim, J. Ahn
ACM ICS 2024
CLAY: CXL-based Scalable NDP Architecture Accelerating Embedding Layers
S. Yun, Hwayong Nam, K. Kyung, J. Park, B. Kim, Y. Kwon, E. Lee, J. Ahn
ASPLOS 2024
TAROT: A CXL SmartNIC-Based Defense Against Multi-bit Errors by Row-Hammer Attacks
C. Song, M. J. Kim, T. Wang, H. Ji, J. Huang, I. Jeong, J. Park, Hwayong Nam, M. Wi, J. Ahn, N. S. Kim
MICRO 2023
How to Kill the Second Bird with One ECC: The Pursuit of Row Hammer Resilient DRAM
M. J. Kim, M. Wi, J. Park, S. Ko, J. Choi, Hwayong Nam, N. S. Kim, J. Ahn, E. Lee
IEEE CAL 2023
X-ray: Discovering DRAM Internal Structure and Error Characteristics by Issuing Memory Commands
Hwayong Nam, S. Baek, M. Wi, M. J. Kim, J. Park, C. Song, N. S. Kim, J. Ahn
IEEE TC 2023
GraNDe: Efficient Near-Data Processing Architecture for Graph Neural Networks
S. Yun, Hwayong Nam, J. Park, B. Kim, J. Ahn, E. Lee
IEEE CAL 2022
GraNDe: Near-Data Processing Architecture with Adaptive Matrix Mapping for Graph Convolutional Networks
S. Yun, B. Kim, J. Park, Hwayong Nam, J. Ahn, E. Lee
Patents
10 applications, all pending
- Memory Controller and Operation Method Thereof (with Samsung Electronics) — US 19/002,383 · CN 202411903289.8 · KR 10-2024-0050775
- Semiconductor Device and Method of Operating the Same — PCT/KR2024/015034 · KR 10-2024-0110034 · KR 10-2024-0117102
- High-Bandwidth Memory Control Using Row-Granularity Read/Write Commands — KR 10-2025-0160771
- High-Bandwidth Memory Control Using Virtual Banks Grouped by Bank Index Across Pseudo-Channels — KR 10-2025-0160770
- Semiconductor Device and Method of Operating the Same — KR 10-2026-0156913 · KR 10-2026-0156914
Technical Skills
- Programming languages — C/C++, Python, CUDA, Verilog, SystemVerilog, Bash
- Memory & hardware — DDR4/DDR5, HBM2E, FPGA-based DRAM test platforms (DRAM-Bender), memory controller design, RowHammer/PRAC, ECC, CXL (Type-2/3 FPGA devices, CHMU), RTL design and synthesis, memory simulators (Ramulator)
- Systems & ML — Linux kernel memory management (page migration, tiering, MGLRU), PMU-based performance profiling, LLM inference profiling
- EDA & FPGA tools — Cadence Xcelium, Synopsys Design Compiler, AMD Vivado, Altera Quartus
Program Committee & Teaching
- Technical Program Committee, HPCA 2027
- Artifact Evaluation Committee, ISPASS 2025
- Teaching Assistant, Programming Methodology, Seoul National University, Spring 2021